This patent specification claims priority and is related to Japanese patent applications, No. JPAP2001-081217 filed on Mar. 21, 2001 and No. 2002-23245 filed on Jan. 31, 2002, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a method and apparatus for digital-to-analog conversion, and more particularly to a method and apparatus for digital-to-analog conversion with an effective pulse width modulation.
2. Discussion of Background
FIG. 1 shows a typical structure of a background digital-to-analog converter that converts digital data into analog data with a pulse width modulation (PWM) technique which is described, for example, in Japanese unexamined utility publications, No. 3 -53042 (1991) and No. 6-13231 (1992).
As shown in FIG. 1, the background digital-to-analog converter (often referred to as a DA converter or a DAC) includes a ring counter (COUNT) 1, a magnitude comparator (COMP) 2, and an RC circuit 3. The ring counter 1 counts inputs of a main clock signal MCLK and outputs clock count information composed of, for example, eight bits whose bit number corresponds to the resolution of the DAC. The resolution of the DAC is 1/256 in this case. A cycle of the main clock MCLK is referred to as Tmclk, and an eight-bit counting cycle of the ring counter 1 is referred to as a pulse width modulation cycle Tpwm. The pulse width modulation cycle Tpwm includes 256 Tmclk cycles of the main clock. The magnitude comparator 2 receives the eight-bit clock count information on input terminals B0-B7, and a data set DSET composed of eight bits, whose number of bits is equal to that of the clock count information, on input terminals A0-A7. The eight-bit data set DSET has a value corresponding to a desired output level and is sent from a central processing unit or (CPU) or the like (not shown).
The background DA converter is a converter used, for example, as a feedback circuit for adjusting a direct current level of an analog signal or as a full-scale or for adjusting a zero-scale level of an analog-to-digital (AD) converter in a control for automatically adjusting a reading level of a reading mechanism in a digital copying machine, a scanner, or the like. The data set DSET applied to the background DA converter is changed in a cycle sufficiently longer than the pulse width modulation cycle Tpwm.
The ring counter 1 counts the main clock MCLK at all times and outputs a count value on the eight-bit output terminals Q0-Q7 to the input terminals B0-B7 of the magnitude comparator 2. The comparator 2 compares the count value with the value of the data set DSET. During the time the count value is smaller than the data set DSET, the comparator 2 outputs a pulse signal Vpwm in a high state which has a pulse width corresponding to the value of the data set DSET, as shown in FIG. 2. The pulse signal Vpwm is smoothed through the RC circuit 3 including a resistor R and a capacitor C, and a resultant analog voltage Vdac in response to the value of the data set DSET is output.
In FIG. 2, Th represent a time length of the pulse signal Vpwm in a high state which is composed of Tmclk multiplied by the value of the data set DSET. T1 represent a time length of the pulse signal Vpwm in a low state which includes Tmclk multiplied by a value of 256 Tmclk subtracted by the data set DSET.
FIG. 3 is a time chart showing a relationship between the pulse signal Vpwm and the analog voltage Vdac in two exemplary cases at the same time. In one case in which waveforms are indicated by solid lines, the value of the data set DSET is set to 128, for example, and the related signal and waveform are labeled with a suffix numeral 128. In the other case in which waveforms are indicated by dotted lines, the value of the data set DSET is set to 64, for example, and the related signal and waveform are labeled with a suffix numeral 64. For example, Vpwm128 indicates as the pulse signal Vpwm in the case where the data set DSET is set to 128, and Vpwm64 indicates as the pulse signal Vpwm in the case where the data set DSET is set to 64. In addition, a mean voltage of the analog voltage Vdac128 is referred to as Vdacm128, and a mean value of the analog voltage Vdac64 is referred to as Vdacm64.
A relationship between the analog voltage Vdac and the value of the data set DSET is expressed by the following equation;
Vdac=(DSET/256)xc3x97(Vhxe2x88x92Vl)+Vl,
where Vh represents the pulse signal Vpwm in a high state and Vl represents the pulse signal Vpwm in a low state.
To maintain the above relationship, an amount of change in the analog voltage Vdac during the time the pulse signal Vpwm in a high state or a low state should necessarily be smaller than a half the resolution of the DAC. For this maintenance, an amount of change in the analog voltage Vdac should satisfy the following relationships (1) and (2):
when the pulse signal Vpwm is in a high state
{Vhxe2x88x92Vdac(0)}xc3x97{1xe2x88x92exp(xe2x88x92Th/xcfx84)} less than ((Vhxe2x88x92Vl)/256)/2,xe2x80x83xe2x80x83(1)
and when the pulse signal Vpwm is in a low state
{Vlxe2x88x92Vdac(1)}xc3x97{1xe2x88x92exp(xe2x88x92Th/xcfx84)} greater than )(Vhxe2x88x92Vl)/256)/2,xe2x80x83xe2x80x83(2)
where Vdac(0) represents a value of the analog voltage Vdac immediately before the pulse signal Vpwm is raised to a high level, Vdac(1) represents a value of the analog voltage Vdac immediately before the pulse signal Vpwm is lowered to a low level, and xcfx84 represents a time constant of the RC circuit. In FIG. 3, an amount of change in the analog voltage Vdac discussed above is referred to as a ripple voltage Vrip-A in the case of 128 DSET and a ripple voltage Vrip-B in the case of 64 DSET.
In the relationships above, when the time constant xcfx84 is far greater than the time length T which is the sum of the time lengths Th and T1, a condition of Th=T1 will give a maximum amount of change in the analog voltage Vdac in the relationship (1) as well as a minimum amount in the relationship (2). In addition, the relationships (1) and (2) are equivalent when the voltage Vl is 0. Therefore, based on the relationship (1), the following relationship can be obtained in consideration of a steady state:
Vh(1xe2x88x920.5)xc3x97{1xe2x88x92exp(xe2x88x92T/2/xcfx84)} less than (Vh/256)/2.
This relationship may be modified to;
Exp(xe2x88x92T/2/xcfx84) greater than 1xe2x88x921/256=255/256,
and further to;
xe2x88x92T/2/xcfx84 greater than ln(255/256).
Finally, the following approximation can be made;
T less than xe2x88x922xc3x97xcfx84xc3x97ln(255/256)≈2xc3x97xcfx84xc3x97(1/256)=xcfx84/128.
When the main clock signal MCLK has a frequency of 10 MHz, the time constant of the RC filter 3 can be calculated as follows;
xcfx84 greater than Txc3x97128=0.1 xcexcsxc3x97256xc3x97128=3.3 ms.
Consequently, when the analog voltage Vdac is changed from 0 to a full scale, for example, it takes an extremely long response time t as;
t=xe2x88x92xcfx84xc3x97ln(1/512)=20.6 ms.
One object of the present invention is to provide a novel digital-to-analog converter for converting an n-bit digital data set to an analog voltage, where n is an arbitrary integer and the n bits include upper nh bits and lower nl bits. Accordingly, in one embodiment of the present invention, a novel digital-to-analog converter includes a signal generator, a low-weighted value manager, and a voltage smoothing circuit. The signal generator is arranged and configured to perform a pulse width modulation based on inputs of a reference clock signal and the upper nh bits of the n-bit digital data set and configured to generate a first pulse-width-modulated signal having a plurality of first pulses having a first pulse width in response to a value of the upper nh bits of the n-bit digital data set and a pwm cycle signal indicating a cycle of a pulse width modulation performed. The low-weighted value manager is arranged and configured to receive the pulse-width-modulated signal, the pwm cycle signal, and the lower nl bits of the n-bit digital data set, configured to divide a pulse width in response to a value of the lower nl bits of the n-bit digital data set into a plurality of fraction pulse widths, to respectively add the plurality of fraction pulse widths to the plurality of first pulses, and to generate a second pulse-width-modulated signal having a plurality of second pulses having the first pulse width and one of the plurality of fraction pulse widths. The voltage smoothing circuit is arranged and configured to smooth the second pulse-width-modulated signal.
Further, another object of the present invention is to provide a novel digital-to-analog converter for converting an n-bit digital data set to an analog voltage, where n is an arbitrary integer and the n bits include upper nh bits and lower nl bits. Accordingly, in one embodiment of the present invention, a novel digital-to-analog converter includes a signal generator, an amplitude regulator, a bottom-level regulator, a voltage adding circuit, and a voltage smoothing circuit. The signal generator is arranged and configured to perform a pulse width modulation based on inputs of a reference clock signal and the lower nl bits of the n-bit digital data set and configured to generate a pulse-width-modulated signal having a plurality of first pulses having a first pulse width in response to a value of the lower nh bits of the n-bit digital data set. The amplitude regulator is arranged and configured to regulate an amplitude of the pulse-width-modulated signal generated by the signal generator. The bottom-level regulator is arranged and configured to receive the upper nh bits of the n-bit digital data set and to regulate a bottom level of a voltage in accordance with a value of the upper nh bits of the n-bits digital data set. The voltage adding circuit is arranged and configured to add the pulse-width-modulated signal having an amplitude regulated by the amplitude regulator to the voltage having a bottom level regulated by the bottom-level regulator and configured to output a composite voltage. The voltage smoothing circuit is arranged and configured to smooth the composite voltage output by the voltage adding circuit.
Further, another object of the present invention is to provide a novel digital-to-analog converter for converting an n-bit digital data set to an analog voltage, where n is an arbitrary integer and the n bits include upper nh bits and lower nl bits. Accordingly, in one embodiment of the present invention, the novel digital-to-analog converter includes a signal generator, a low-weighted value manager, a level regulator, and a voltage smoothing circuit. The signal generator is arranged and configured to perform a pulse width modulation based on inputs of a reference clock signal and the upper nh bits of the n-bit digital data set and configured to generate a first pulse-width-modulated signal having a plurality of first pulses having a first pulse width in response to a value of the upper nh bits of the n-bit digital data set and a pwm cycle signal indicating a cycle of a pulse width modulation performed. The low-weighted value manager is arranged and configured to receive the pulse-width-modulated signal, the pwm cycle signal, and the lower nl bits of the n-bit digital data set configured to generate multi-bit pulse-width-modulated signals including the pulse-width-modulated signal as a least significant bit and the lower nl bits of the n-bit digital data set. The level regulator is arranged and configured to receive the multi-bit pulse-width-modulated signals and to output an analog voltage with an upper level regulated in response to a value of the multi-bit pulse-width-modulated signals. The voltage smoothing circuit is arranged and configured to smooth the analog voltage output by the level regulator.
Further, another object of the present invention is to provide a novel method of digital-to-analog conversion for converting an n-bit digital data set to an analog voltage, where n is an arbitrary integer and the n bits include upper nh bits and lower nl bits. Accordingly, in one embodiment of the present invention, a novel method of digital-to-analog conversion includes the steps of performing, dividing, adding, and smoothing. The performing step performs a pulse width modulation based on inputs of a reference clock signal and the upper nh bits of the n-bit digital data set and generates a first pulse-width-modulated signal having a plurality of first pulses having a first pulse width in response to a value of the upper nh bits of the n-bit digital data set and a pwm cycle signal indicating a cycle of a pulse width modulation performed. The dividing step divides a pulse width in response to a value of the lower nl bits of the n-bit digital data set into a plurality of fraction pulse widths. The adding step adds respectively the plurality of fraction pulse widths to the plurality of first pulses to output a second pulse-width-modulated signal having a plurality of second pulses having the first pulse width and one of the plurality of fraction pulse widths. The smoothing step smoothes the second pulse-width-modulated signal output in the adding step.
Further, one object of the present invention is to provide a novel method of digital-to-analog conversion converts n-bit digital data set to an analog voltage, where n is an arbitrary integer and the n bits include upper nh bits and lower nl bits. Accordingly, in one embodiment of the present invention, the novel method of digital-to-analog conversion includes the steps of performing, regulating, determining, adding, and smoothing. The performing step performs a pulse width modulation based on inputs of a reference clock signal and the lower nl bits of the n-bit digital data set and generates a pulse-width-modulated signal having a plurality of first pulses having a first pulse width in response to a value of the lower nh bits of the n-bit digital data set. The regulating step regulates an amplitude of the pulse-width-modulated signal generated in the performing step. The determining step determines a bottom level of a voltage in accordance with a value of the upper nh bits of the n-bits digital data set. The adding step adds the pulse-width-modulated signal having an amplitude regulated in the regulating step to the voltage having a bottom level determined in the determining step to output a composite voltage. The smoothing step smoothes the composite voltage output in the adding step.
Further, one object of the present invention is to provide a novel method of digital-to-analog conversion converts n-bit digital data set to an analog voltage, where n is an arbitrary integer and the n bits include upper nh bits and lower nl bits. Accordingly in one embodiment of the present invention, the novel method for digital-to-analog conversion includes the steps of performing, generating, outputting, and smoothing. The performing step performs a pulse width modulation based on inputs of a reference clock signal and the upper nh bits of the n-bit digital data set to generate a first pulse-width-modulated signal having a plurality of first pulses having a first pulse width in response to a value of the upper nh bits of the n-bit digital data set and a pwm cycle signal indicating a cycle of a pulse width modulation performed. The generating step generates multi-bit pulse-width-modulated signals including the pulse-width-modulated signal as a least significant bit and the lower nl bits of the n-bit digital data set. The outputting step outputs an analog voltage with an upper level regulated in response to a value of the multi-bit pulse-width-modulated signals. The smoothing step smoothes the analog voltage output in the outputting means.